1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device, and more particularly to a nonvolatile semiconductor memory device, such as a flash memory, having a floating gate electrode.
2. Description of the Related Art
A nonvolatile semiconductor device, such as a flash memory, having a floating gate electrode is expected to be useful in the future as a replacement candidate for a magnetic memory medium such as a hard disk or a floppy disk for the reasons of nonvolatility, low power consumption, high level of integration and the possibility of low cost per bit.
Each memory cell of the above kind of nonvolatile semiconductor memory device consists of a memory cell transistor, and, as shown in FIG. 3, each transistor is constituted of a tunned oxide film 302 on a P-type silicon substrate 301 formed by thin film formation technology due to silicon thermal oxidation technology and CVD method, photolithography technology and thin film dry etching technology, a polycrystalline silicon double layer gate consisting of a floating gate 303 formed of polycrystalline silicon, a layer insulating film 304 and a control gate 305 formed of polycrystalline silicon, and a source diffused layer 307 and a drain diffused layer 306 formed using phosphorus or arsenic ion implantation technology.
The floating gate 303 is a gate for varying the threshold of the memory cell transistor from the control gate 305. When hot electrons are accumulated in the floating gate 303, a positive potential given to the control gate 305 is canceled by the hot electrons accumulated in the floating gate 303, so that the threshold of the memory cell transistor from the control gate 305 becomes higher compared with the state in which hot electrons are not accumulated.
An injection of the hot electrons to the floating gate 303 is accomplished by applying 10 V, 5 V and 0 V to the control gate 305, drain 306 and source 307, respectively. Thus, some of the electrons migrating in the channel of the memory cell transistor reach the floating gate 303 passing through the tunnel oxide film 302, and are accumulated there. Such a state in which hot electrons are accumulated in the floating gate 303 represents the data write state. On the contrary, the ejection of the hot electrons from the floating gate 303 brings the drain 306 to an electrically open condition (floating condition), which can be realized by applying 5 V to the source 307 and -16 V to the control gate 305. With this arrangement, Fowler-Nordheim current which is the tunneling current of the tunnel oxide film 302 in the overlapped region of the source diffused layer 307 and the floating gate 303 is generated to expel the electrons from the floating gate 303 via the tunneling oxide film 302. Such a state in which there is accumulated no hot electron in the floating gate 303 represents the data erase state.
In addition, data read is performed by applying 5 V, 1 V and 0 V to the control gate 305, drain 306 and source 307, respectively. At that time, if the memory cell transistor is in the write state, namely, if it is in a state where hot electrons are accumulated in the floating gate 303, the voltage of 5 V given to the control gate 305 is canceled by the hot electrons so that the memory cell transistor does not go to the conducting state, whereas, if the memory cell transistor is in the erase state, namely, if it is in the state where hot electrons are not accumulated in the floating gate 303, the memory cell transistor goes to the conducting state due to the voltage given to the control gate 305. Accordingly, data read from the memory transistor can be carried out by detecting such conduction or nonconduction.
In FIG. 4 is shown an example of the conventional nonvolatile semiconductor memory device. In the nonvolatile semiconductor memory device shown in the figure, for ease of description, there is illustrated a case in which the memory device comprises memory cell transistors M11 to M43 divided into blocks 401 and 402 according to the unit of batch erasure of data. Bit lines B1 to B3 which are connected in common to the drain electrodes of the memory cell transistors M11, M21, M31 and M41, memory cell transistors M12, M22, M32 and M42 and memory cell transistors M13, M23, M33 and M43, respectively. Word lines W1 to W4 which are connected in common to the control gate electrodes of the memory cell transistors M11, M12 and M13, memory cell transistors M21, M22 and M23, memory cell transistors M31, M32 and M33 and memory cell transistors M41, M42 and M43, respectively. Source lines S1 to S4 which are connected in common to the source electrodes of the memory cell transistors M11, M12 and M13, memory cell transistors M21, M22 and M23, memory cell transistors M31, M32 and M33 and memory cell transistors M41, M42 and M43, respectively. A column decoder 403 which decodes column addresses AC in response to a write control signal C and controls so as to select one of the bit lines B1 to B3, a row decoder 404 which decodes row addresses AR and controls so as to select one of the word lines W1 to W4, and a source line control circuit 405 which controls the voltages of the source lines S1 and S2, and S3 and S4 of the blocks 401 and 402, respectively, in response to write and erase of data.
Next, the operation of the memory device will be described. In writing data to the memory cell transistor M11 which is the object of write, 10 V, 5 V and 0 V are applied to the word line W1, the bit line B1 and the source line S1, respectively, which are connected to the memory cell transistor M11. The other word lines W2 to W4 and the other source lines S2 to S4 are supplied with 0 V and the other bit lines B2 and B3 are brought to the open state.
As a result, the control gate, the drain and the source of the memory cell transistor M11 which is the write object are supplied with 10 V, 5 V and 0 V, respectively, so that hot electrons are injected to the floating gate of the memory cell transistor M11, and the device is ready to perform writing.
However, if the memory cell transistor M21, M31 or M41 which shares the bit line with the memory cell transistor M11, is already in the write state, it is given 5 V to its drain diffused layer through the bit line B1 at the time of writing data to the memory cell transistor M11, so that there is generated a strong electric field between the floating gate and the drain diffused layer of the memory cell transistor which is already in the write state.
Therefore, an electric field distorts the energy band in the overlapped region of the floating gate and the drain diffused layer. This distortion gives rise to the drain disturbance phenomenon in which the electrons and the holes of the electron-hole pairs created by the energy band distortion are injected to the drain diffused layer and the floating gate, respectively (Anirban Roy, Reliability Physics 30th Annual Proceedings, 1992, pp. 68-75). When the drain disturbance phenomenon occurs, the data is converted from the write state to the erase state because of the decrease in the quantity of accumulated charge in the floating gate.
Since a memory cell transistor in the write state is subjected to the drain disturbance phenomenon whenever the write operation is performed to a memory transistor which shares the same bit line, the length of time subjected to the drain disturbance phenomenon can be represented by, the number of memory cell transistors on a common bit line X number of times of data write to memory cell transistors on the common bit line X data write time. In reality, however, the number of times of data rewrite to the memory cell transistors on the common bit line amounts to about one hundred thousand times to one million times so that it is impossible to hold the write data.
Suppression of the drain disturbance can be accomplished by setting the voltage applied to the bit line B1 for driving the memory cell transistor M11 to be lower than 5 V. Moreover, the resistance to the drain disturbance of the memory cell transistor can be improved while maintaining the rate of data write by optimizing the structure of the drain (Akinori Kodama, Technical Digest of International Electron Devices Meeting, 1991, pp. 303-306).
However, when the voltage applied to the bit line B1 for driving the memory cell transistor M11 is set low at 4 V, for example, in order to suppress the drain disturbance, the rate of data write to the memory cell transistor M11 becomes low by about one order of magnitude compared with the case of application of 5 V to the bit line, sharply deteriorating the write efficiency.
Further, when the drain structure is optimized for the purpose of suppressing the drain disturbance, the drain structure becomes extremely complicated, making the manufacturing process complicated and long.